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PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
Rev. 03 -- 27 April 2010 Product data sheet
1. Product profile
1.1 General description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low on-state resistance Simple gate drive required due to low gate charge Suitable for high frequency applications due to fast switching characteristics
1.3 Applications
DC-to-DC convertors Lithium-ion battery applications Notebook computers Portable equipment
1.4 Quick reference data
Table 1. Symbol VDS ID Ptot Quick reference data Parameter drain-source voltage drain current total power dissipation Conditions Tj 25 C; Tj 150 C Tsp = 25 C; VGS = 10 V; see Figure 1; see Figure 3 Tsp = 25 C; see Figure 2
[1]
Min -
Typ -
Max Unit 30 V 10.4 A 3.57 W
Static characteristics RDSon drain-source on-state VGS = 10 V; ID = 8 A; resistance Tj = 25 C; see Figure 9; see Figure 10 gate-drain charge VGS = 5 V; ID = 5 A; VDS = 15 V; Tj = 25 C; see Figure 11 17 20 m
Dynamic characteristics QGD 3.9 nC
[1]
Single device conducting.
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 4 5 6 7 8 Pinning information Symbol Description S1 G1 S2 G2 D2 D2 D1 D1 source1 gate1 source2 gate2 drain2 drain2 drain1 drain
1 4 S1 G1 S2 G2
mbk725
Simplified outline
8 5
Graphic symbol
D1 D1 D2 D2
SOT96-1 (SO8)
3. Ordering information
Table 3. Ordering information Package Name PHKD13N03LT SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current Tsp = 100 C; VGS = 10 V; see Figure 1 Tsp = 25 C; VGS = 10 V; see Figure 1; see Figure 3 IDM Ptot Tstg Tj IS ISM
[1]
[1] [1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions Tj 25 C; Tj 150 C Tj 25 C; Tj 150 C; RGS = 20 k Min -20 -55 -55 Tsp = 25 C Tsp = 25 C; tp 10 s; pulsed
[1] [1]
Typ -
Max 30 30 20 6.6 10.4 42 3.57 150 150 3.2 42
Unit V V V A A A W C C A A
peak drain current total power dissipation storage temperature junction temperature source current peak source current
Single device conducting.
Tsp = 25 C; tp 10 s; pulsed; see Figure 3 Tsp = 25 C; see Figure 2
[1]
Source-drain diode -
PHKD13N03LT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
2 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
120 Ider (%) 80
03aa25
120 Pder (%) 80
03aa17
40
40
0 0 50 100 150 Tsp (C) 200
0 0 50 100 150 Tsp (C) 200
Fig 1.
Normalized continuous drain current as a function of solder point temperature
Fig 2.
Normalized total power dissipation as a function of solder point temperature
003aaa368
102 ID (A) Limit RDSon = VDS / ID
10
t p = 10 s
1 ms 10 ms DC 1 100 ms
10-1 10-1
1
10
VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHKD13N03LT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
3 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-sp) Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to solder point thermal resistance from junction to ambient Conditions see Figure 4 minimum footprint; mounted on a printed-circuit board Min Typ 70 Max 35 Unit K/W K/W
102 Zth(j-sp) (K/W) = 0.5 10 0.2 0.1 0.05 1 0.02 single pulse
P
003aaa415
=
tp T
tp T
t
10-1 10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
4 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = -55 C ID = 250 A; VGS = 0 V; Tj = 25 C ID = 250 A; VDS = VGS; Tj = -55 C; see Figure 8 ID = 250 A; VDS = VGS; Tj = 150 C; see Figure 8 ID = 250 A; VDS = VGS; Tj = 25 C; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 24 V; VGS = 0 V; Tj = 25 C VDS = 24 V; VGS = 0 V; Tj = 100 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 8 A; Tj = 150 C; see Figure 9; see Figure 10 VGS = 4.5 V; ID = 7 A; Tj = 25 C; see Figure 9 VGS = 10 V; ID = 8 A; Tj = 25 C; see Figure 9; see Figure 10 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 7 A; VGS = 0 V; Tj = 25 C; see Figure 13 IS = 7 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 30 V; Tj = 25 C VDS = 15 V; RL = 10 ; VGS = 10 V; RG(ext) = 6 ; Tj = 25 C; ID = 1.5 A VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 12 ID = 5 A; VDS = 15 V; VGS = 5 V; Tj = 25 C; see Figure 11 10.7 2.7 3.9 752 200 130 6 7 23 11 0.86 25 5 1.1 nC nC nC pF pF pF ns ns ns ns V ns nC Min 27 30 0.5 1 Typ 1.5 21 17 Max 2.2 2 1 5 100 100 34 26 20 Unit V V V V V A A nA nA m m m
Static characteristics
Source-drain diode
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
5 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
10 ID (A) 8
003aaa325
10 V 5 V
3V
VGS (V) = 2.8 V
10 ID (A) 8
003aaa326
VDS > ID x RDSon
2.7 V 6 2.6 V 4 2.5 V 2 2.4 V 2.3 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 0 1 2 VGS (V) 3 2 Tj = 150 C 25 C 4 6
Fig 5.
Output characteristics: drain current as a function of drain-source voltage; typical values
003aaa426
Fig 6.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
2.5
03aa33
10-1 ID (A) 10-2
VGS(th) (V) 2 max
10-3 min 10-4 typ max
1.5
typ
1
min
10-5
0.5
10-6 0 1 2 VGS (V) 3
0 -60
0
60
120
Tj (C)
180
Fig 7.
Sub-threshold drain current as a function of gate-source voltage
Fig 8.
Gate-source threshold voltage as a function of junction temperature
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
6 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
80 2.5 V RDSon (m) 60 2.6 V
003aaa327
2 a 1.5
03aa27
2.8 V
40 3V
1
20
4V 5V 10 V VGS (V) =
0.5
0 0 2 4 6 8 ID (A) 10
0 -60
0
60
120
Tj (C)
180
Fig 9.
Drain-source on-state resistance as a function of drain current; typical values
5
003aaa330
Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature
104 C (pF) 103
003aaa328
VGS (V) 4
3
Ciss
2 102 1
Coss Crss
0 0 5 10 QG (nC) 15
10 10-1
1
10 VDS (V)
102
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
7 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
5 IS (A) 4
003aaa329
3
2
1
150 C
Tj = 25 C
0 0.2
0.4
0.6
0.8 VSD (V)
1
Fig 13. Source current as a function of source-drain voltage; typical values
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
8 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z
8 5
Q A2 A1 pin 1 index Lp
1 4
(A 3)
A
L wM detail X
e
bp
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
o
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8 o 0
Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-18
Fig 14. Package outline SOT96-1 (SO8)
PHKD13N03LT All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
9 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history Release date 20100427 Data sheet status Product data sheet Product data sheet Product data Change notice Supersedes PHKD13N03LT_2 PHKD13N03LT-01 Document ID PHKD13N03LT_3 Modifications: PHKD13N03LT_2 PHKD13N03LT-01 (9397 750 11612)
*
Various changes to content.
20090306 20030623
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
10 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
9.3
Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 03 -- 27 April 2010
11 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, IC-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE -- are trademarks of NXP B.V. HD Radio and HD Radio logo -- are trademarks of iBiquity Digital Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PHKD13N03LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
12 of 13
NXP Semiconductors
PHKD13N03LT
Dual N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 April 2010 Document identifier: PHKD13N03LT

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